To reduce pin count in an integrated circuit (IC), serial programming is often used. Because serial programming data is loaded into the IC in a continuous stream, only a single data input pin is required for programming. Typically, the programming data is loaded into a shift register within the IC. FIG. 1 shows a cascaded shift register 100 that has a typical register structure for a serially programmable IC. Shift register 100 includes flip flops 111, 112, 113, and 114, each of which includes an input terminal D, an output terminal Q, and a clock terminal CK. Output terminal Q of flip flop 111 is connected to input terminal D of flip flop 112, output terminal Q of flip flop 112 is connected to input terminal D of flip flop 113, and output terminal Q of flip flop 113 is connected to input terminal D of flip flop 114 to form the cascaded structure. Meanwhile, each clock terminal CK of flip-flops 111–114 is coupled to receive a clock signal CLOCK.
On each pulse of clock signal CLOCK, an input data value DIN is loaded into flip flop 111, the data previously stored in flip flop 111 is loaded into flip flop 112, the data previously stored in flip flop 112 is loaded into flip flop 113, and the data previously stored in flip flop 113 is loaded into flip flop 114. The data previously stored in flip-flop 114 is provided as an output data value DOUT. In this manner, serial data is shifted into (and out of) shift register 100. The data stored in shift register 100 can also be read out in parallel from the output terminal Qs of each of flip flops 111–114, as data values Q1–Q4, respectively.
Serially programmed memory ICs use this serial-in-parallel-out (SIPO) capability of a cascaded shift register to improve programming efficiency. In a typical memory IC, programming an individual memory cell in a memory array takes much longer than shifting data into a shift register. This is especially true for non-volatile memories such as electrically erasable programmable read only memories (EEPROMs) and FLASH memories. For example, 14 milliseconds (ms) might be required to program a memory cell in an EEPROM or FLASH memory. In contrast, filling a shift register with new data only requires a number of clock cycles equal to the number of flip flops in the shift register—e.g., if the system clock is running at 22 MHz and the shift register is a 4096-bit shift register, filling the shift register would only require 0.19 ms (=4096/22×106). Therefore, to minimize programming time, serial data is shifted into the shift register, and the contents of the shift register are then programmed into a particular address of the memory array as a single word. Since the memory cell programming for an entire row of the memory array can be performed in parallel, this “page mode” programming technique can significantly reduce overall programming time.
FIG. 2A shows a serially programmable memory IC 200 that is programmable via a JTAG (Joint Test Action Group) interface. JTAG refers to IEEE standard 1149.1-1990 (includes IEEE Std 1149.1a-1993), published by the Institute of Electrical and Electronics Engineers, Inc. on Oct. 21, 1993 under ISBN 1-55937-350-4, herein incorporated by reference. IEEE standard 1149.1 defines a boundary scan test method for detecting bad connections (shorted pins, open pins, bad traces, etc.) in circuit boards. IC 200 includes a test access port (TAP port) 201, a TAP controller 202, an M×N memory array 220, a bitline latch 221, an instruction register 230, an instruction decoder 231, a register circuit 240, and an output control circuit 250. Register circuit 240 includes a “full width” (i.e., the same width as memory array 220) data register 241 and a bypass register 242.
All JTAG compliant devices such as IC 200 include test access port (TAP port) 201 and TAP controller 202 to provide the desired boundary scan functionality. TAP port 201 includes three input connections for receiving a test data input signal TDI, a test mode select signal TMS, and a test clock signal TCK. The TAP port also includes an output connection through which a test data output signal TDO is transmitted. A TAP port sometimes includes an optional reset pin to reset the test logic.
TAP port 201 provides signals TMS and TCK to tap controller 202, while providing signal TDI to instruction register 230 and register circuit 240. TAP controller 202 is a state machine controlled by signal TMS that runs the JTAG hardware through two paths—an instruction register path (“IR path”) during which data from signal TDI is loaded into instruction register 201, and a data register path (“DR path”) during which data from signal TDI is loaded into register circuit 240. A clock signal CLK provided by TAP controller 202 (based on test clock signal TCK) clocks the data into the appropriate data or instruction registers. Instruction decoder 231 converts the data stored in instruction register 230 into an instruction INSTR that specifies the type of test or action to be performed using the data stored in register circuit 240. Data can be shifted into data register 241 or can be “passed through” IC 200 via bypass register 242. Output control circuit 250 provides test data output signal TDO at TAP port 201 from one of instruction register 230, data register 241, or bypass register 242, depending on control signals SEL_IN and SEL_TAP from instruction decoder 231 and TAP controller 202, respectively.
The behavior of TAP controller 201 in response to test mode select signal TMS is described in detail in section 5 of IEEE standard 1149.1. Basically, as signal TMS is switched between logic HIGH and LOW levels, TAP controller 201 is transitioned between its various states in response to clock signal TCK. These states determine how data at TAP controller 201 and in instruction register 230 and register circuit 240 are handled. When TAP controller 201 is operating in the IR path, the value of an instruction register state IR_ST manages the loading of data into (and out of) instruction register 230, and when TAP controller 201 is operating in the DR path, the value of a data control state DR_ST manages the loading of data into (and out of) the registers of register circuit 240.
Although the IEEE standard 1149.1 was originally developed for testing purposes, the standardized JTAG interface has become popular as a programming interface because of its ready availability on many ICs. “JTAG-programmable” ICs are serially programmed through the TDI input connection of TAP controller 201. M×N memory array 220 is made up of M rows (i.e., rows WM−1 through W0) and N columns (i.e., columns CN−1 through C0) of memory cells. Program data is shifted into data register 241, and this data is latched into bitline latch 221 and then programmed into memory array 220 in a parallel programming operation (page mode). Since data register 241 has the same width as memory array 220, each programming operation fills a full row of memory array 220. In this manner, the TAP port can also be used for programming purposes, thereby minimizing the number of pins required for an IC.
However, as memory arrays continue to increase in size, the denser memory structures become more susceptible to memory defects (such as a column short, bad interconnect, etc.). Therefore, to maintain a high production yield, it becomes increasingly desirable to provide redundancy in a memory array—i.e., include extra columns that can be used to replace defective columns. In the absence of such redundancy, a single bad memory cell can render an entire memory array unusable. Conventionally addressed memory arrays incorporate such redundant columns by simply addressing the appropriate redundant column instead of the defective column. However, in conventional serially programmable memory arrays, this type of random access is not available, making redundancy extremely difficult to incorporate.
For example, in FIG. 2A, columns C1 and C0 could be redundant columns to be used if there are defects in any of columns CN−1 through C2 (which would then represent the “primary memory region” of memory array 220—i.e., the portion of memory array 220 in which data would be stored in the absence of array defects). In such an arrangement, replacing a defective column with column C0 would require that the flip flop in data register 241 associated with column C0 receive the data originally intended for the flip flop associated with the defective column. However, the flip-flops in a shift register (i.e., data register 241) are hardwired in a predetermined order, and so cannot be easily reordered to incorporate the redundant column in place of the defective column.
To overcome this limitation, conventional ICs sometimes include redundancy logic that counts clock cycles as data is shifted into the shift register. The redundancy logic uses the clock counts to determine whether a particular data bit is associated with a defective column, and if so, transfers that data bit to a redundant column. To function properly, this type of redundancy logic must know exactly when the program data begins shifting into the data register. However, in many cases, such program data timing knowledge is not available, so conventional redundancy logic cannot be used.
For example, multiple JTAG-compliant ICs are typically connected into a continuous chain so that the boundary scan operation can be performed. FIG. 2B shows a chain of JTAG-compliant ICs 200A, 200B, 200C, and 200D. Each of ICs 200A–200D includes a data input pin TDI_P, a data output pin TDO_P, a mode select pin TMS_P, and a clock pin TCK_P (as described with respect to FIG. 2A). The mode select pins TMS_P of ICs 200A–200D are commonly coupled to receive mode select signal TMS, while the clock pins TCK_P of ICs 200A–200D are commonly coupled to receive clock signal TCK. In contrast, the data pins (TDI_P and TDO_P) of ICs 200A–200D are serially connected—i.e., pin TDO_P of IC 200A is connected to pin TDI_P of IC 200B, pin TDO_P of IC 200B is connected to pin TDI_P of IC 200C, and pin TDO_P of IC 200C is connected to pin TDI_P of IC 200D. Therefore, data from signal TDI can be shifted sequentially into the data registers of ICs 200A–200D (and data from those registers can be shifted out as signal TDO). This serial arrangement beneficially allows a continuous stream of test data to be shifted through ICs 200A–200D to perform boundary scan operations.
A conventional programming flow for ICs 200A–200D is shown in FIG. 2C. In a “LOAD DATA-SHIFT INSTRUCTION” step 291, an instruction that enables shifting data to be programmed into the devices, is loaded into the instruction registers of ICs 200A–200D in a continuous bitstream. The standard TAP controller states in the associated IR path are listed next to step 291 for reference purposes. Then, in a “SHIFT FULL WIDTH PROGRAM DATA” step 292, the program data for page mode programming of each of ICs 200A–200D is loaded into the ICs in a continuous bitstream. Once again, the standard TAP controller states in the associated DR path are listed next to step 292 for reference purposes. Finally, in a “LOAD PROGRAMMING INSTRUCTION” step 293, an instruction is loaded into the instruction registers of ICs 200A–200D in a continuous bitstream (the TAP controller states in the associated IR path are listed next to step 293 for reference). This initiates a “PROGRAM MEMORY ARRAY ROW” step 294 in each of the 4 ICs. During step 294 a selected row in each of the memory arrays of ICs 200A–200D is programmed from the data register of the IC. In this manner, the JTAG interface can be used to program ICs 200A–200D. However, because conventional JTAG-based programming methods involve shifting the programming data through the chain of ICs in a single continuous stream, none of the individual ICs has knowledge of when its own program data is being loaded into its shift register. Only when program data has filled the entire chain of ICs can an individual IC “know” its specific program data. Therefore, conventional redundancy logic cannot be used in JTAG-compliant ICs.
Accordingly, it is desirable to provide a system and method for incorporating redundancy into a JTAG-programmable IC without requiring specific knowledge about the timing of program data.